(1) Field of the Invention
The present invention relates to the fabrication semiconductor integrated circuits, and more particularly to a method of fabricating random access memory (DRAM) devices, having stacked capacitors with an additional polysilicon plug to reduce the aspect ratio for capacitor node contact openings while increasing capacitance.
(2) Description of the Prior Art
Advances in Ultra Large Scale Integration (ULSI) technologies are dramatically increasing the circuit density on the semiconductor chip. This increase in density is due in part to advances in high-resolution photolithography and anisotropic plasma etching in which the directional ion etching results in essentially bias-free replication of the photoresist image in the underlying patterned layers, such as in polysilicon and insulating oxide layers and the like.
One such circuit type where this high-resolution processing is of particular importance is the dynamic random access memory (DRAM) circuit. This DRAM circuit is used extensively in the electronics industry, and particularly in the computer industry for electrical data storage. The DRAM circuits consist of an array of individual memory cells, each cell consisting of an access transistor, usually a field effect transistor (FET), and a single storage capacitor. Information is stored on the cell as charge on the capacitor, which represents a unit of data (bit), and is accessed by read/write circuits on the periphery of the DRAM chip. After the year 2000 the number of these cells on a DRAM chip is expected to exceed a gigabit. To achieve this high density and still maintain a reasonable chip size, the individual cells on the chip must be significantly reduced in size. As these individual memory cells decrease in size, so must the area on the cell that the storage capacitor occupies. The reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain an acceptable signal-to-noise level, and circuits require shorter refresh cycle times to retain the necessary charge level. One method of overcoming this size problem is to build stacked capacitors that extend vertically over the cell areas to increase the electrode capacitor area while confining the capacitor within the cell area.
However, as the minimum feature sizes decrease to less than a quarter-micrometer (0.25 um), it becomes increasing difficult to built reliable stacked capacitors without increasing process complexity and manufacturing cost. One process complexity is the need to etch contact holes in insulators with increasing aspect ratios (depth/width). It is difficult to etch these deep holes without over-etching that damages the substrate causing excessive junction leakage at the capacitor node contact.
For these submicrometer devices it is also important to provide planar surfaces to facilitate the formation of high resolution photoresist etch masks that require a more shallow depth of focus (DOF) during the photoresist exposure. Planar surfaces are also required because of the very directional etching, since patterning layers, such as polysilicon and metals, by directional etching can otherwise result in unwanted residue at steps (recesses) on non-planar surfaces. However, planarizing process, such as chemical-mechanical polishing or planarizing etch backs, are time consuming and costly. Therefore it is desirable to minimize the number of planarizing steps and to reduce the aspect ratio for contact holes on DRAM circuits.
Numerous methods of making DRAM circuits with stacked capacitors having increased capacitance have been reported in the literature. The following U.S. patents describe several methods for making stacked capacitors. Wang et al. in U.S. Pat. No. 5,702,989 describe a method for making a DRAM using a single polysilicon plug as the capacitor node contact and also serves as a center column in the capacitor to increase capacitance. However, this single plug requires etching very deep contact contacts with very high aspect ratios (depth/width) and is difficult to achieve without excessive over etching in the insulating layer. Another approach is described by Chao in U.S. Pat. No. 5,863,821 in which a contact hole is etched through a multilayer to the substrate. This is also difficult to achieve without over-etching. Tseng in U.S. Pat. Nos. 5,854,105 and 5,843,821 describe methods for making DRAMs with single polysilicon plugs in a planar insulating on which are fabricated stacked capacitors. However, further process would require an insulating layer over the capacitors that would need to be planarized. In U.S. Pat. No. 5,888,865 Lin describes a method for making a DRAM capacitor using a single polysilicon plug that also serves as a portion of the stacked capacitor. However, Lin etches contact holes through a relatively thick multilayer to the substrate which can result in over-etch and substrate damage (leakage currents).
However, there is still a need to improve the fabrication of DRAM devices with high capacitance for future product generation below the 0.25 um feature sizes and to make the process more manufacturable and cost effective.